The present Rev A specimen-current PCB, headers, feedthrough and firmware are not qualified for this elevated-voltage assembly. The diagrams specify electrical roles; component selection, insulation, discharge protection and firmware must be engineered before construction. Voltage examples are illustrative, not approved ratings.
01 / CONNECTION MAP
Follow the electron signal.
VACUUM → FLOATING → GROUND
The collector goes to SUM. The positive bias goes to FCOM. Powered, unsaturated amplifier feedback holds the collector near FCOM while measuring the current.
SYSTEM OVERVIEWThree electrical references. One measured current.
01 INSIDE VACUUM
Emitted electronsMixed SE + BSE · no current gain
SUM → guarded feedthrough
02 FLOATING AT +VC
▷LMC662Current → voltage
→
▦ADC + MCUVoltage → data
Battery power · ±5 V locally · ADC 3.3 V
FCOM ← bias supply positive
03 GROUNDED READOUT
→ ←
Scan ESP32 / PCFibre pair · requests + readings
PE Chamber & outer enclosure
KEY CONNECTIONBias + → FCOM. Never directly to collector / SUM.
Three references. One measured current.
SUM is the sensitive collector input. FCOM is the elevated local common and guard. PE is the grounded chamber and accessible outer enclosure. The vacuum wall and the electrical insulation boundary are separate.
Detailed connection schematicPin numbers, feedback, guard, power and optical boundary+
Functional nets, not dimensions or insulation ratings. On small screens, scroll the detailed schematic horizontally.
SUM. Guard current must bypass the measurement. Keep guard outside the collection opening.
04 · PE
Protective earth / chamber reference
Chamber, mechanical stage, accessible outer enclosure and designated outer shield. Bias-supply return references this point as its manufacturer specifies.
FCOM inner guard. Maintain a dedicated protective-earth bond.
Specimen
Conductive specimen contact
Grounded stage in this collector-only arrangement.
SUM. An uncoated insulating specimen still needs charging control.
These are the existing board’s connector functions mapped to a future floating revision. They are not instructions to energize the present board at +VC. Its original ground and enclosure connections belong to the specimen-current option.
Rev A connector reference · changes needed before a floating build
Existing connector
Function in a future floating revision
Required change / check
J1 pin 1 · SUM
Collector signal → U1A pin 2
Replace/select the input connection and vacuum feedthrough for the full bias and transient environment.
J1 pin 2 · AGND
FCOM inner guard
Remove the original chamber bond in the redesigned assembly. Provide a separate PE outer shield; a grounded BNC shell is not an FCOM guard.
J2 pins 1 / 2 / 3
+5F / FCOM / −5F
All power sources float. Reassess layout, connector access, mounting and insulation to earth.
J3 pin 1
Floating MCU common → FCOM
The existing grounded scan ESP32 stays on the other side of the fibre link.
J3 pins 3 / 4
Local SDA / SCL only
Choose local MCU pins and implement its ADC driver and optical protocol. These are not copper links to the scan controller.
J3 pin 2 / pin 5
3.3 V reference output / optional ALERT
Do not power the MCU or optics from pin 2; provide a separate local regulator. Leave pin 5 unconnected in the initial polling design.
LMC662 and ADC signal path reference
For LMC662AIMX/NOPB, SOIC-8: U1A pin 2 = −IN, pin 3 = +IN, pin 1 = OUT; supply pin 8 = +5F, pin 4 = −5F. U1B pin 5 receives the local 1.32 V reference; pin 6 sums through 40.2 kΩ from U1A output and 10 kΩ from pin 7. Pin 7 drives the protected/filtered ADC A0 input. ADC A1 receives local 1.65 V. All references are relative to FCOM.
ADS1115 differential A0−A1 at address 0x48, ±0.256 V and 128 SPS is the existing reference configuration. Differential measurement does not allow either analog pin outside the local 0–3.3 V supply range. Calibrate zero and gain in the actual assembly.
The inner guard is at FCOM and inaccessible. The accessible outer case stays at PE. Choose a guarded feedthrough or appropriately rated triax arrangement with independent signal, guard and outer shield. Voltage withstand alone does not establish low leakage.
Specify insulation, spacings, discharge paths and transient protection for the complete assembly. Put supply bleeders on FCOM-to-PE as designed, never SUM-to-PE. Do not put an ordinary leaky clamp diode on SUM.
DATA & TIMING
A new acquisition handshake.
The grounded ESP32 sets X/Y and waits for settling. It sends a pixel-ID acquisition request over fibre. The floating MCU starts fresh ADC conversions and returns pixel ID, raw code and status. The ESP32 accepts the matching result before moving on.
Timeouts, stale IDs, clipping or loss of detector power must abort acquisition and request beam blanking. Existing direct-I²C firmware does not implement this link; optical isolation is not a beam safety interlock.
03 / SIGNAL CALCULATOR
Put numbers to the signal.
Explore an assumed net collector current with fixed 100 MΩ / 10 pF feedback and the existing attenuator/ADC values. The bias range below is illustrative, not an approved operating range. Changing bias does not predict collection efficiency or create current gain.
FCOM relative to chamber+200 VBias supply → local common+5F / −5F relative to chamber+205 V / +195 VStill ±5 V across local supply referencesTIA output relative to FCOM+1 mV+200.001 V relative to chamberADC differential change from zero−248.756 µVΔV = −(10 / 40.2) × I × 100 MΩUnwanted DC leakage magnitude2 pA DCI = VC / RleakDisplacement-current amplitude3.142 pA peakIpk = 2πf C Vripple,pk
Illustrative calculations; hardware measurements are required.
Calculation assumptions & limits
Positive net deposited-electron equivalent current gives VTIA−FCOM = InetRf. Conventional current has the opposite direction. The ADC differential change is negative because of the inverting conditioner. At ±0.256 V, its nominal 0.314 pA/code step is quantization, not sensitivity; the nominal uncalibrated zero is about −1.642 mV.
The leakage example uses residual SUM-to-chamber insulation, not guard-to-chamber insulation. Guard leakage is intended to bypass SUM. The ripple result is input displacement current before amplifier/ADC filtering; it is a sine-wave peak, not RMS broadband noise. The calculator does not combine DC offset with AC amplitude or model op-amp noise, drift, charging, field distortion, surface yields or image resolution. Baseline subtraction cannot remove random noise or changing leakage.
04 / VERIFY THE SIGNAL
Five checks before trusting a reading.
After a qualified assembly design, commission at zero bias with the beam blanked. Increase bias only after local power, protection and optical communication are established. Allow displacement currents to settle after every bias change.
Calibrate within the floating section.
Use an independently measured calibration resistor and quiet local voltage source referenced to FCOM: I = V / R. Check both polarities, gain and clipping at zero bias. For example, a +1 V local source through 100 MΩ injects +10 nA conventional current and drives the TIA negative. Remove the calibration source before electron collection.
Repeat under intended bias.
Keep the calibration entirely local; compare gain, offset, noise and settling at zero and elevated common potential. No grounded oscilloscope, USB cable, charger or programming lead may bridge the floating boundary.
Measure the real collector background.
Connect the feedthrough and collector, beam blanked. Log dark current and drift with pumps, gun heater, scan drivers and local digital/optical activity operating. Measure the full input capacitance and check for oscillation or slow recovery.
Try to produce a false image.
Run a raster with the beam blanked and then with electrons intercepted upstream. Scan-correlated structure identifies electrical pickup. Repeat with bias fixed; acquire after bias ramps have settled.
Establish repeatable electron contrast.
Start with a grounded conductive specimen. Compare repeated scans, measured beam currents and settled collector-bias settings. Record raw codes, dark zero, calibration, bias, timing and any overload or communication fault.
Example acceptance target
For an intended 10 pA contrast signal: aim for ≤1 pA RMS input-referred noise at the chosen pixel timing, with drift and systematic errors separately bounded below the useful contrast. These are proposed test targets. Nothing on this page establishes that the hardware meets them.
05 / COMPARE METHODS
Choose where you collect the current.
Specimen current
Biased collector proposal
Current enters amplifier from
Insulated conductive specimen holder
Separate metal collector receiving emitted electrons
Amplifier common
Near chamber ground
FCOM at positive collector bias
Specimen connection
Only through the current input
Grounded conductive contact in this arrangement
Data path
Direct local I²C to the scan ESP32
Local ADC controller plus optical request/data link
Signal meaning
Net specimen absorption
Net collector current; mixed SE/BSE and possible chamber background
Acceleration improves attraction and changes landing energy; a plain metal collector has no intrinsic charge multiplication. Electrons that miss it or hit the guard are not counted. Electrons escaping the collector alter the net reading. Collector geometry, electric-field disturbance of the primary beam and an insulating specimen’s charging all still need investigation.
Sources support the operating principles, not qualification of this proposed assembly. This battery / fibre arrangement remains a concept. The separate 12 / 24 V board guide supplies prototype CAD and optical-UART firmware; neither option has measured hardware or micrographs.