DAC80502 / DUAL 16-BIT

Place the beam.
One precise step at a time.

A dedicated X/Y command board for the ESP32, synchronized with the LMC662 specimen-current detector. The scan amplifiers use a shared, buffered 1.25 V center.

Program the scan ↗Detector & current readout →

01 / ELECTRICAL CONNECTIONS

From digital coordinates to plate voltage.

NEW LOW-VOLTAGE MODULE · REV A

The DAC board stays outside vacuum. Its X/Y outputs connect to the external differential scan amplifiers; the LMC662 detector remains on its separate board.

Scan board connector	Connect to
J1.1 / J1.2	Clean 3.3 V input / signal ground
J1.3 / J1.4 / J1.5	ESP32 GPIO18 SCLK / GPIO23 SDIN / GPIO27 SYNC
J1.6 → J3.1	GPIO25 → external active-high blank request; J3.2 ground
J2.1 / J2.3	X / Y amplifier command inputs
J2.5	Buffered 1.25 V center → both amplifier reference inputs
J2.2 / J2.4 / J2.6	Signal ground alongside each analog output

02 / POSITIONING ≠ IMAGE RESOLUTION

See what the extra bits change.

DACBeam voltage 3 kVPeak scan amplitude (V)External amplifier gain (V/V)Pixels per side

Changing gain here represents changing the physical scan amplifier. This calculator is independent of your saved run.

Nominal step / code—

Scanned field width—

Requested raster spacing—

Distinct raster positions—

Formula, derivation & sources

ΔVDAC = VFS / 2ᴺ. Subtracting the center and amplifying gives ΔVplates = A × ΔVDAC. The ideal plate sensitivity is S = eL(D + L/2)/(gpv), so Δx = S × ΔVplates. Here L = 20 mm, D = 15 mm and g = 10 mm; p and v use relativistic beam energy. The raster includes both endpoints: requested spacing is field width / (pixels − 1).

DAC80502 uses 65,536 intervals, with code 65,535 one interval below full scale. These are nominal values; noise, nonlinearity, offsets, gain error, drift, fringing and beam blur require separate characterization.

TI transfer equation ↗ · OpenStax electric force ↗ · JEOL probe-size limits ↗

03 / NATIVE DESIGN FILES

A separate board for the scan commands.

UNBUILT PROTOTYPE

The module contains the dual DAC, decoupling, matched midpoint divider, OPA333 buffer, output isolation resistors and blank-request pull-up. Its WSON DAC needs reflow assembly.

Complete KiCad design package ↓ ZIP Electrical schematic ↗ PDF Gerbers & drill files ↓ ZIP Component BOM ↓ CSV Module cost allowance ↓ CSV Assembly & bench checks ↗Design verification report ↗ JSON

External scan amplifiers are still to be selected. Passed CAD checks establish connectivity and layout rules; they do not establish measured scan accuracy.

04 / BRING-UP ORDER

Check position commands before scanning.

Inspect and power the module. Keep the beam blanked. Verify 3.3 V input and the firmware configuration before connecting the external drivers.
Initialize while blanked. SPI mode 1 at 1 MHz; CONFIG = 0x0000, GAIN = 0x0103, SYNC = 0x0003. Write A/B midpoint code 32768, then software LDAC (TRIGGER = 0x0010). Allow 100 ms after configuration for the reference and center circuit to settle.
Measure the low-voltage outputs. After initialization, code 32768 should be near 1.25 V. Test 16384 and 49152 near 0.625 V and 1.875 V. Allow warm-up, then measure the center under its real load; calibrate offset and gain. The low-cost matched network does not guarantee 16-bit midpoint accuracy.
Check the complete driver chain. With gain 100 and a ±20 V differential scan, the DAC spans about 1.05–1.45 V. Verify polarity, voltage range, paired updates, noise and settling at the actual plate load. The board does not supply plate-drive voltages.
Acquire with the current detector. Keep the existing 5 ms beam-on settling and 10 ms acquisition window initially. Record the blanked zero with z; s starts and x stops/blanks. Compare repeat scans before pursuing finer features.